In modern electronic systems, a frequency synthesizer is often used to generate high frequency outputs from a fixed low frequency input. The performance of the frequency synthesizer is usually limited by a frequency divider and a voltage-controlled oscillator (VCO) included in the frequency synthesizer.
Programmable frequency dividers by even factors (e.g., 2*N) are often used to generate high frequency outputs from the fixed low frequency input.
FIG. 1 illustrates a conventional frequency divider system. As shown, a frequency divider system 100 includes a periodic counter 110 and a frequency divider 120.
A duty cycle of a short pulse SP that is output from the periodic counter 110 is, in general, not close to 50% and, therefore, cannot be used in most applications.
In order to solve this issue, the frequency divider 120 is generally a frequency divider by two. The frequency divider by two 120 changes its output with every pulse from the periodic counter 110, which is described below. The frequency divider by two 120 is often implemented with a single flip-flop.
The periodic counter 110 receives division factor control bits div_by <m:0> and an input clock signal clk. The periodic counter 110 is configured to output a short pulse SP after every N input clock periods. The frequency divider by two 120 is configured to receive the short pulse SP and output a 50% duty cycle output. Due to the use of the frequency divider by two 120, a total division factor is limited to even factors (2*N) only.
FIG. 2 illustrates a timing diagram for the frequency divider system 100. As illustrated, a short pulse SP is output for every N (four is used only as an example) rising edge of the clock signal clk. For every rising edge of the short pulse SP, the output signal changes from a low level to a high level or vice versa.
Conventionally, a counting frequency is doubled to achieve a frequency divider by an odd division factor. Unfortunately, maximum counting frequency is limited by technology used and, in some cases, cannot be doubled. Additionally, even when counting frequency can be doubled, it leads to excessive power and, in some cases, also area penalties.
Frequency dividers may be implemented in many different electronic systems.